Conventional programmable memories utilize a matrix of common collector memory cells which provide a current path between a supply node to a bit line. Each of the cells is comprised of a bipolar transistor with the collector connected to the supply node and the emitter connected through a fuse to the bit line. The logic state of the memory cell is determined by the condition of the fuse, with one state being represented by an intact fuse and the other logic state being represented by an open fuse.
When a memory cell is selected, the bit line is connected to a sense amp which is essentially a current source. The sense amp determines if current is being drawn from the emitter of the memory cell attached to the bit line. This current is sensed and the voltage on a corresponding output pin changed to correspond to the sensed logic state of the selected memory cell.
During the transition between logic states of the sensed memory cell, it is necessary to change the voltage on the output pin. This output pin has a predetermined amount of distributed capacitance associated therewith. When a transition occurs, the capacitance on the output pin must either be discharged or charged by the output buffer circuitry. If the output pin undergoes a transition from a low voltage to a high voltage, the capacitance on the output must be charged to a high voltage. This requires a predetermined amount of current to be sourced from the output buffer circuitry to the output pin. In order to source this current, it is necessary for additional current to be drawn from the supply pin and through the various "runs" on the circuit in order to supply this current. In high speed devices, this charge time may be as little as two nanoseconds.
Transients on the supply line create problems that occur during charging up of the output pin when making a logic transition. In conventional devices, the collectors of the transistors utilized in the memory cell are all connected directly to the supply node. Therefore, when the supply voltage is pulled low, the collectors of the transistors and memory cells are also pulled low. When the circuit recovers, the collector voltages return to the supply voltage level. However, due to the parasitic capacitance between the collector of the transistors in the memory cells and the bit line, the bit line tends to be pulled high, thus resulting in the possibility of outputting a false logic state.
In view of the above disadvantages, it is desirable to isolate the memory cells from transients on the supply line that result from capacitive loading of the output pins.